View 74F2993_970930.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
74F299 8-bit universal shift/storage register (3-State)
Product data Supersedes data of 1990 Mar 01 2003 Feb 05
Philips Semiconductors
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
FEATURES
* Common parallel I/O for reduced pin count * Additional serial inputs and outputs for expansion * Four operating modes: Shift left, shift right, load and store * 3-State outputs for bus-oriented applications
DESCRIPTION
The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-LOW Master Reset is used to reset the register. The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times, relative to the rising edge of clock are observed. A HIGH signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation.
PIN CONFIGURATION
S0 OE0 OE1 I/O6 I/O4 I/O2 I/O0 Q0 MR 1 2 3 4 5 6 7 8 9 20 VCC 19 S1 18 DS7 17 Q7 16 I/O7 15 I/O5 14 I/O3 13 I/O1 12 CP 11 DS0
GND 10
SF00865
TYPE 74F299
TYPICAL fMAX 115 MHz
TYPICAL SUPPLY CURRENT (TOTAL) 58 mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5 V 10%, Tamb = 0 C to +70 C N74F299N N74F299D PKG DWG #
20-pin plastic DIP 20-pin plastic SOL
SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DS0 DS7 S0, S1 CP MR OE0, OE1 Q0, Q7 I/On Serial data input for right shift Serial data input for left shift Mode select inputs Clock pulse input (Active rising edge) Asynchronous Master Reset input (Active LOW) Output Enable input (Active LOW) Serial outputs Multiplexed parallel data inputs DESCRIPTION 74F(U.L.) HIGH / LOW 1.0 / 1.0 1.0 / 1.0 1.0 / 2.0 1.0 / 1.0 1.0 / 1.0 1.0 / 1.0 50 / 33 3.5 / 1.0 LOAD VALUE HIGH / LOW 20 A / 0.6 mA 20 A / 0.6 mA 20 A / 1.2 mA 20 A / 0.6 mA 20 A / 0.6 mA 20 A / 0.6 mA 1.0 mA / 20 mA 70 A / 0.6 mA 3.0 mA / 24 mA
3-State parallel outputs 150 / 40 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20 A in the HIGH State and 0.6 mA in the LOW state.
2003 Feb 05
2
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
LOGIC SYMBOL
11 18
LOGIC SYMBOL (IEEE/IEC)
SRG8 9 2 DS0 DS7 3 1 19 12 11 7 0 1 4R & 3EN13 M 0 3
1 19 12 9 2 3
S0 S1 CP MR OE0 OE1 Q0 I/00 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
C4/1 /2 1, 4D 3, 4D 5, 13 Z5 Z6 8
13
3, 4D 6, 13
6 VCC = Pin 20 GND = Pin 10 8 7 13 6 14 5 15 4 16 17 14 5 15 4 16 18 3, 4D 12, 13 2, 4D Z12 17
SF00866
SF00890
FUNCTION TABLE
INPUTS OEn L L L L L H L X = = = = MR L H H H H S1 X H L H L X INPUTS S0 X H H L L X CP X X X OPERATING MODE Asynchronous Reset; Q0 - Q7 = LOW Parallel load; I/On Qn (I/On outputs disabled) Shift right; DS0 Q0, Q0 Q1, etc. Shift left; DS7 Q7, Q7 Q6, etc. Hold Outputs in High-Z
H X HIGH voltage level LOW voltage level Don't care LOW-to-HIGH clock transition
2003 Feb 05
3
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
LOGIC DIAGRAM
DS7 18 OE0 OE1 19 RD 1 2 3 CP D S1 S0 Q 16 I/O7 17 Q7
CP D RD Q 4 I/O6
CP D RD Q 15 I/O5
CP D RD Q 5 I/O4
CP D RD Q 14 I/O3
CP D RD Q 6 I/O2
CP D RD Q 13 I/O1
CP D 11 12 9 RD 8 Q 7 I/O0
DS0 CP VCC = Pin 20 GND = Pin 10 MR
Q0
SF00868
2003 Feb 05
4
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IO OUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in HIGH output state Current applied to output in LOW output state Operating free-air temperature range Storage temperature Q0, Q7 I/On PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +VCC 40 48 0 to +70 -65 to +150 UNIT V V mA V mA mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IO OH Supply voltage HIGH-level input voltage LOW-level input voltage Input clamp current HIGH-level HIGH level output current Q0, Q7 I/On LOW-level LOW level output current Operating free-air temperature range Q0, Q7 I/On 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 -3 20 24 70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA mA mA C UNIT
IO OL Tamb
2003 Feb 05
5
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS1 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 2.4 2.7 3.3 0.35 0.35 -0.73 0.50 0.50 -1.2 100 1 20 -1.2 -0.6 70 -0.6 -60 55 VCC = MAX 70 65 -150 60 90 95 3.4 TYP2 MAX UNIT V V V V V V V A mA A mA mA A mA mA mA mA
Q0, Q0 Q7 VO OH HIGH-level HIGH level output voltage I/On
VCC = MIN, VIL = MAX MAX, VIH = MIN VCC = MIN, VIL = MAX MAX, VIH = MIN
IO = -1 mA 1 OH
IO = -3 mA 3 OH
VO OL VIK II
LOW-level LOW level output voltage Input clamp voltage In ut Input current at maximum input voltage HIGH-level input current LOW level input current LOW-level Off-state output current, HIGH-level voltage applied Off-state output current LOW-level voltage applied Short-circuit output current3 ICCH others I/On except I/On S0, S1 others I/On only
IO = MAX OL VCC = MIN, II = IIK
VCC = MAX, VI = 7.0 V VCC = 5.5V, VI = 5.5 V VCC = MAX, VI = 2.7 V VCC = MAX, VI = 0 5 V MAX 0.5 VCC = MAX, VO = 2.7 V VCC = MAX, VO = 0.5 V VCC = MAX
IIH IIL IIH + IOZH IIL + IOZL IOS
ICC
Supply current (total)
ICCL ICCZ
mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5 V, Tamb = 25 C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
2003 Feb 05
6
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 C VCC = +5.0 V CL = 50 pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Q0 or Q7 Propagation delay CP to I/On Propagation delay MR to Q0 or Q7 Propagation delay MR to I/On Output Enable time Sn, OE to I/On Output Disable time Sn, OE to I/On I/O Qn Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 1 70 85 4.0 4.5 4.0 4.0 5.5 5.5 3.5 4.0 2.5 1.5 TYP 100 115 5.0 6.0 6.0 6.5 7.5 7.5 6.0 7.5 4.5 2.5 7.5 8.0 9.0 9.0 9.5 10.0 8.0 10.0 7.0 5.5 MAX Tamb = 0 C to +70 C VCC = +5.0 V 10% CL = 50 pF, RL = 500 MIN 70 85 3.5 4.5 4.0 4.0 5.5 5.5 3.5 4.0 2.5 1.5 8.5 8.5 10.0 10.0 10.5 10.5 9.0 11.0 8.0 6.5 MAX MHz MHz ns ns ns ns ns ns ns ns ns ns UNIT
AC SET-UP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 C VCC = +5.0 V CL = 50 pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Set-up time, HIGH or LOW S0 or S1 to CP Hold time, HIGH or LOW S0 or S1 to CP Set-up time, HIGH or LOW I/On, DSL or DSR to CP Hold time, HIGH or LOW I/On, DSL or DSR to CP CP Pulse width, HIGH or LOW MR Pulse width, LOW Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 6.5 6.5 0 0 3.5 3.5 0 0 5.0 4.5 4.5 4.0 TYP MAX Tamb = 0 C to +70 C VCC = +5.0 V 10% CL = 50 pF, RL = 500 MIN 7.5 7.5 0 0 4.0 4.0 0 0 5.0 4.5 4.5 4.0 MAX ns ns ns ns ns ns ns ns ns ns ns UNIT
2003 Feb 05
7
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
AC WAVEFORMS
For all waveforms, VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX CP VM tW(H) tPHL Q0, Q7, I/On VM tW(L) tPLH tPHL VM Q0, Q7, I/On VM VM CP MR VM tW(L) VM tREC VM
SF00869
SF00870
Waveform 1. Propagation delay, clock input to output, clock width, and maximum clock frequency
Waveform 2. Master Reset pulse width, Master Reset to output delay, and Master Reset to clock recovery time
S0, S1, I/On DSL, DSR CP
VM ts(H) VM
VM th(H)
VM ts(L)
VM th(L) VM
Sn, OEn
VM tPZH
VM tPHZ VM 0V VOH -0.3V
I/On
SF00871
SF00872
Waveform 3. Set-up and hold times
Waveform 4. 3-State Output Enable time to HIGH level and Output Disable time from HIGH level
Sn, OEn
VM tPZL
VM tPLZ VM VOL +0.3V
I/On
SF00873
Waveform 5. 3-State Output Enable time to LOW level and Output Disable time from LOW level
2003 Feb 05
8
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
2003 Feb 05
9
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
2003 Feb 05
10
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
2003 Feb 05
11
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
REVISION HISTORY
Rev _3 Date 20030205 Description Product data (9397 750 11037); ECN 853-0365 29307 of 17 December 2002. Supersedes Product specification (9397 750 05117) of 01 March 1990.
* Delete all references to DB package. Package option was discontinued.
_2 19900301 Product specification (9397 750 05117); ECN 853-0365 29307 of 01 March 1990.
Modifications:
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 02-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11037
Philips Semiconductors
2003 Feb 05 12

▲Up To Search▲

Price & Availability of 74F2993

	To Download 74F2993 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .